Timing circuit for actuating a load in accurate relationship to two inputs



May 24, 1966 1. W. LEMON, JR 3,253,157

TIMING CIRCUIT FOR ACTUATING A LOAD IN ACCURATE RELATIONSHIP To TwolNPUTs Filed Feb. 8, 1965 United States Patent() 3,253,157 THMING CIRCUTFUR ACTUATING A LOAD IN ACCURATE RELATINSHIP T TWO INPUTS .lohn W.Lemon, Jr., Berkley, Mich., assignor to Robotron Corporation, Detroit,Mich., a corporation of Michigan Filed Feb. 8, 1963, Ser. No. 257,175 9Claims. (Cl. 307-885) This invention relates to electrical timingcircuits and particularly to a type thereof for producing an outputsignal pulse as the result of the occurrence of at least two events, oneof which is the supply of an input pulse t0 the timing circuit.

In many types of timing circuits it is desirable to provide an outputsignal pulse immediately upon the occurrence of an input pulse but onlyafter the elapsing of a predetermined minimum period of time followingIthe occurrence of another event. In many kinds of electronic timers anelectrical potential is caused to charge a capacitor and the timerequired to place a predetermined charge on said capacitor functions toestablish said minimum period of time. At some time after the capacitorattains such charge, means are employed to discharge said capacitor andthe pulse obtained from such discharge is used as the output signal.

If the charging period for the capacitor is relatively long, such as atime period corresponding to several or more cycles of a 60-cycle A.C.source, known circuits are reasonably accurate and variations in theprecise moment at which a triggering pulse occurs will not materiallyaffect the accuracy of the point at which the output signal istransmitted. However, Where the capacitor is caused to charge in a veryshort period of time, such as a time period corresponding to one cycleor less of a 60icycle A.C. source, previous known circuits fortriggering the discharge of such a capacitor have either been complex,hence expensive to manufacture and maintain or they have had somethingless than fully satisfactory accuracy.

One particular circuit in which the present invention may be used toadvantage is the circuit disclosed in my application Serial No. 187,165,filed April ll, 1962,

wherein a condenser is caused to charge to a preselected value at whichpoint it breaks down the resistance of a unijunction transistor andcurrent from said condenser then flows through said unijunctiontransistor and the desired signal pulse can be taken from any convenientpoint in the discharge circuit. However, because of variations in thelevels at which a unijunction transistor will become conductive, due tovariations between unijunction transistors or due to variations in oneunijunction transistor at different periods during its useful life, theinterval between the pulses produced in this manner may not be exactlyequal.

Accordingly, the objects of the invention include:

(l) To provide an electrical circuit for producing an output pulse inresponse to a suitably supplied input pulse, successive output pulsesbeing separated from each other by an accurately predetermined, minimumperiod of time.

(2) To provide a circuit, as aforesaid, which can be operated to providethe desired output pulses accurately at any desired time following apredetermined minimum time period.

(3) To provide a circuit, as aforesaid, wherein said predeterminedminimum charging time may be as short as a time period corresponding toone-quarter cycle, or even Patented May 24, 1966 ICC is of full cyclesand will hence effect a more accurate control than if it were permittedto effect function changes during a cycle.

(6) To provide a circuit, as aforesaid, in which the minimum period oftime is established by the time required to charge a capacitor.

(7) To provide a circuit, as aforesaid, in which both the minimum andmaximum potential levels of the capacitor are accurately controlled inorder to accurately control the time it takes to charge the capacitor.

(8) To provide a circuit, as aforesaid, which can be accurately adjustedto suit the characteristics of the individual components which comprisethe circuit so as t-o accommodate variations in the characteristics ofsaid components.

Other objects and purposes of the invention will be apparent to personsacquainted with circuits of this general type upon reading the followingdisclosure and inspecting the accompanying drawings.

In the drawings:

FIGURE 1 is a diagram of a preferred circuit embodying the invention.

FIGURE 2 is a time-vs.voltage diagram of the charge on the emitter ofthe unijunction transistor of the circuit of FIGURE 1 which alsocorresponds approximately to the charge on the capacitor.

General description In general, the invention provides a circuit whichcontrols the time at which a load is energized in response to twooccurrences, one of which involves charging a capacitor to such a levelthat it can make it possible for conduction of a unijunction transistorto occur when a firing pulse is supplied to one of the bases thereof,and the other of which is the actual supply of the ring pulses itself.The capacitor must be charged to the aforementioned level before thering pulse can be effective to cause conduction and, thus, firing pulsessupplied prior to such charging are ineffective.

The general principle upon which the circuit is based will be apparentfrom a consideration of FIGURE 2 which shows a time-vs.voltage diagramof the voltage on the emitter of the unijunction transistor at varioustimes during the operation of the circuit. The broken line 1 indicatesthe emitter voltage necessary to cause conduction of the unijunctiontransistor under the bias conditions which exist at all times exceptwhen a firing pulse is supplied to one base of said transistor. Thesolid line 2 indicates the potential on the unijunction emitter which isresponsive to the charge on the hereinafter-mentioned capacitor 27. The.chain dotted line 3 indicates the minimum potential level which existson such emitter at the start of a timing operation. This is determinedby the charge which exists upon another capacitor 24. The minimum chargeon the capacitor 27 is indicated by the line 20. The chain dotted line25 indicates the charge on the capacitor 27 as the operation progresses.The circuit of the invention involves charging the first-mentionedcapacitor 27 and thereby increasing the emitter voltage beginning at thetime indicated at point 10 as indicated by the portion 4 of line 2 untila maximum emitter voltage level is established at the time indicated atpoint 5. This maximum emitter voltage level which correspondsapproximately to a maximum charge on the capacitor 27 is maintained, asindicated by the flat portion 6, until a ring pulse P occurs. Such pulsechanges the bias conditions on the unijunction transistor such that themaximum emitter voltage is then sufficient to cause conduction of theunijunction transistor. When such occurs, the capacitor 27 dischargesand the emitter voltage decreases sharply as indicated by the portion 7.transistor then ceasesto conduct.

It is a fundamental purpose of the circuit to insure that the charge onthe capacitor 27 be increased to its maximum level during a preciselycontrolled time in order to insure a fixed minimum time period betweensuccessive firings of the unijunction transistor. It may happen that thecapacitor 24 may discharge below the line 3 when the unijunctiontransistor conducts, as indicated by the portion 8 and, therefore, thecircuit provides means for insuring that the capacitor 24 is charged asindicated by portion 9 to the fixed level indicated by line 3 before thenext charging thereof to the maximum level begins.

The unijunction Detailed description Referring to FIGURE 1, the circuitcomprises a pair of terminals 11 and 12. Terminal 11 is connected to thepositive side of a source of D.C., or rectified A.C., potential whilethe terminal 12 is connected to ground. A first conductor 13 isconnected to the terminal 11. A rheostat 15, a resistance 17 and afurther rectifier 18 are connected in series between the conductor 13and a conductor 21. The conductor 21 has a pair of junction points 22and 23 therein and it also has a capacitor '24 connected therein betweenthe junction point 23 and a conductor 26. The conductor 26 is connectedto the terminal 12.

One side of a capacitor 27 is connected to a junction point 28 which islocated between the resistance 17 and the rectifier 18. The other sideof the capacitor 27 is connected by a conductor 29 to the conductor 26.Thus, when the hereinafter referred to switch 14 is opened andtransistor 56 is non-conductive, the capacitor 27 is charged through acircuit including line 13, rheostat 15, resistance 17 and conductor 29.

Junction point 23 is connected through a rectifier 31 to a junctionpoint 32 thence through a resistance '33 to the conductor 26. Thecircui-t which comprises the rectifier 18, rectifier 31 and resistance33 is connected in parallel with the capacitor 27 between the junctionpoint 28 and the conductor 26. The value to which capacitor 27 can becharged is determined by the potential drop which exists across thecircuit elements which are connected in parallel therewith. Thus, thisparallel circuit establishes the maximum charge which can be placed onthe capacitor 27 and this charge is proportional to the charge indicatedby the portion 6 in FIGURE 2. The rate of charging of the capacitor 27is determined by the setting of the rheostat which is selected so as toprovide the desired time period for charging the capacitor. Thus, thesetting of the rheostat 15 establishes the time period between points 16and 5 on the diagram of FIG- URE 2.

A further conductor 36 is connected to the input terminal 11 and aplurality of subcircuits are connected in parallel between it and theconductor 26. The first subcircuit is a voltage divider circuit and itis comprised of a resistance 37 which is connected to the junction point32 and thence through the resistance 33 to the conductor 26. Theresistances 33 and 37, therefore, establish a fixed voltage at point 32and thus establish the maximum potential (line 6 in FIGURE 2) which canexist at point 22.

The second subcircuit also is a voltage divider circuit and it iscomprised of series connected resistances 38 and 39. A junction point 41between resistances 38 and 39 is connected to a rectifier 42 which inturn is connected to the junction point 22. The resistances '38 and 39are so related to each other that the potential at junction point 41and, therefore, the potential at junction point 22 has a minimum levelcorresponding to the level indicated by the line 3 in FIGURE 2. Thus, ifthe potential at point 22 `drops below the level indicated by the line 3in FIGURE 2, it is quickly brought up to such level by ow of energythrough the voltage divider circuit including the resistance 38.

The third subcircuit comprises a resistance 43 which is connectedthrough a junction point 44 to one base B2 of a Yunijunction transistor46. The other base B1 of the transistor 46 is connected to a junctionpoint 47, thence through a. resistance 4S to the conductor 26. Theresistances 43 and 48 provide a bias on the unijunction transistor 46 atsuch a level that the emitter voltage necessary to cause conduction vofsaid -transistor is at the high level indicated by the broken line 1 inFIG- URE 2, the resistance 48 being appreciably less than the resistance43. 'Since the voltage on the emitter of unijunction transistor 46, asindicated by the solid line 2 in FIGURE 2, never reaches this level, thetransistor 46 is normally nonconductive. The emitter of the transistor46 is connected to the junction point 22.

A pulse generator 51 is connected through a coupling capacitor 52 to thejunction point 44. The pulse generator 51 may be of any suitableconventional type and may supply firing pulses to the junction point 44at either regular or irregular intervals. When such pulses do occur, asindicated at P in FIGURE 2, they lower the biasing potential on theunijunction transistor 46 and, therefore, lower the required emitterfiring voltage so that the potential on the emitter then is sufiicientto effect conduction of the transistor 46. Thus, if the potential on theemitter is at the level indicated by portion 6 of line 2 in FIGURE 2,which corresponds to the fully charged condi-tion of the capacitor 27,the transistor conducts forthwith. Desirably, the initiating pulsesupplied by the pulse generator 51 is as short and sharp as practicable(subject to the characteristics of the unijunction) and of the desiredamplitude and polarity in order to provide the exact timing.

When the transistor 46 becomes conductive, the capacitor 27 dischargesthrough the rectifier 18, conductor 21, point 22, transistor 46 andresistance 48 to conductor 26. This provides an output pulse at thejunction point 47. Thus, the occurrence of the output pulse iscontrolled by two events, (l) the charging of the capacitor 27 to such alevel that the transistor 46 can become conductive when an input pulseis supplied at junction point 44, and (2) the actual occurrence of theinput pulse at junction point 44. Thus, the time that it takes to chargethe capacitor 27 -to its maximum level, that is, the time between points16 'and S, establishes the earliest point at which the transistor 46 canbecome conductive and the next input pulse appearing at junction point44 determines the actual time at which conduction occurs.

Capacitor 24 is provided in order to keep the unijunction transistor 46conductive long enough to insure complete discharge of the capacitor 27.Tests have shown that if this capacitor is not provided, `the transistor46 will fire and then will be extinguished before the capacitor 27 isfully discharged. The capacitor 24 charges simultaneously with thecapacitor 27 and when the transsistor 46 is fired it discharges throughthe transistor and keeps same conductive for a sufficient period of timeto allow current to begin to fiow through diode 18 to fully dischargecapacitor 27.

While a variety of different loads can be actuated by pulses supplied tojunction point 47, a particularly advantageous load, which cooperateswith the capacitor 27, is shown for purposes of illustration. This loadis comprised of a bistable circuit including two transistors 56 and 57arranged so that the transistor 57 is normally conductive and transistor56 is nonconductive. A conductor 58 connects 4the positive side of thecapacitor 27 to circuitry including a resistance 59 and a rectifier 61which are connected in series to a junction point 62 thence to thecollector of a transistor 56.

A rectifier 72 and a switch 14 are connected in series between junctionpoints 75 and 70. Junction point 75 is located between resistance 59 andrectifier 61 and junction point 70 is connected to the emitter oftransistor 56. The switch 14, therefore, is connected in parallel withtransistor 56 and provides an alternate path for charging the capacitor27 to the minimum level indicated by line 2() in FIGURE 2. Hence wheneither transistor 56 is conductive or switch 14 is closed, the capacitor27 is charged to the minimum level. When both transistor 56 isnonconductive and switch 14 is open, then the capacitor 27 is charged toits maximum level through rheostat 15, resistance 17 and conductor 29.

A resistance 69 is connected between junction point 76 and line 26.Additional bistable circuits, one of which is shown generally at 78, canbe added to the line 77 and junction point 76.

When a pulse appears at point 47, transistor 57 becomes nonconductiveand transistor 56 becomes conductive. Further load devices responsive tooperation of the bistable circuits may be connected to conductors 63 and63a.

A resetting device may be incorporated in theload shown wherein saiddevice includes the capacitors 81 and 82, the resistances 83, 84, 85, 86and 87 and the switch 88. The capacitor S1 connects the lower end of thediode 61 to the series circuit comprising the base of the transistor56a, the resistance 86, and the primary terminal of the switch 88. Thecapacitor 82 connects the output end of the transistor 56a to the seriesstring comprising the resistance 83, the base of the transistor 56, theresistance 84, and the ground line 26. The resistance 85 is connectedbetween the base of the transistor 57 and the primary terminal of theswitch 88. The resistance `87 connects the base of the transistor 57a toground. Connection of the switch 88 to the positive source 89 causes thetransistors 57 and 56a to conduct continuously in the reset condition.Connection of the switch 88 to ground requires initiation by opening ofthe switch 14 to cause the circuit to cycle in its intended manner.

Any residual charge on the capactor 27 will be permitted to discharge tothe predetermined minimum level which is proportional to the levelindicated by line when the transistor 56 4is conductive or switch 14 isclos-ed. Thus, any variations in the predetermined minimum level ofcharge in the capacitor 27 are eliminated.

Operario-n The operation of the circuit has been indicated before butsame will be briefly repeated in order to insure a oompleteunderstanding of the invention.

When the switch 14 is closed the capacitor 27 will be at its minimumcharge level, indicated by line- 20 and, therefore, the potential on theemitter of the unijunction transistor 46 will be maintained at the levelindicated by the line 3 due to the charge on capacitor 24. Further, thebias on the unijunction transistor 46 is such that the emitter potentialnecessary to cause conduction thereof is substantially above the actualemitter potential. Thus, the unijunction transistor 46 is nonconductive.Pulses supplied by the pulse generator 51 at this time are ineffectiveto cause conduction of the transistor 46 because they donot reduce thebias to such a level that the actual emitter voltage is sufficient tocause conduction thereof.

When the switch 14 is opened (transistor 56 being nonconductive), thecapacitor 27 commences to charge at a predetermined rate as determinedby Ithe setting of the potentiometer 15. This effects a rise in thelevel of the emitter voltage as indicated by the portion 4 of the solidline 2 in FIGURE 2. When the voltage reaches the level indicated by theportion 6 in FIGURE 2, further charging of the capacitor 27 and,therefore, further raising of the potential at the emitter is prevented(by the escape thereof through the resistance 33) so that the actualemitter potential is maintained at this maximum level. This level issuch that it is not sufficient under the normal biasing conditionsexisting on the transistor 46 to effect conduction of the transistor.However, when the next lfiring pulse P is supplied by the pulsegenerator 51, this modifies the biasing conditions on the transistor 46so that th-e emitter voltage necessary to cause conduction thereof isdecreased as indicated in FIGURE 2. The firing pulse P has suficientamplitude to reduce the emitter voltage necessary to cause conductionwell below the actual emitter voltage indicated by portion 6. Therefore,minor variations in the level indicated by lin-e 1 which may be causedby differences between transistors do not appreciably affect theoperation. Thus, the emitter voltage necessary to cause conduction ofthe transistor is present on the emitter thereof so that the transistor46 conducts forthwith. When such occurs, the charges on the capacitors27 and 24 are discharged to their minimum levels through the transistor46 and this provides an output pulse at junction point 47 which is theoutput of the circuit of the present invention. Such output is suppliedto the load shown and makes transistor 56- conductive and transistor 57nonconductive. This also reverses the conductive condition of thetransistors of circuit 78. In addition, any further load devicesconnected to conductors 63- and 63a are actuated.

If the charge on the capacitor 24 should drop below the minimum level,corresponding to the potential on point 22 indicated by line 3, thecharge on the capacitor 24 is immediately raised to a value (line 3)corresponding to the minimum emitter voltage. Since the transistor 56 isconductive, the capacitor 27 will be maintained at its minimum chargelevel even though switch 14 remains open. The charge on capacitor 27 isclose to the potential at point 70.

In this fashion, by insuring a tix-ed minimum and fixed maximum chargeon the capacitor 27, it is possible to accurately control the minimumtime period between the closing of the switch and the firing of theunijunction transistor 46.

The capacitor charging period which can be accommodated by the circuitof the invention can be extremely small, such as a time periodcorresponding to one-quarter of a 60-cycle A.C. supply potential. Whilethe shortest timing interval output will be equal to the spacing of thepulses supplied to junction point 44, the circuit will time longerperiods triggering synchronously with these pulses equally well.

It will be noted that the capacitor 24 is char-ged and dischargedsimultaneously with capacitor 27. Therefore, in appropriate cases thecapacitor 27 and line 29 can be eliminated and the capacitor 24 can -beused to measure the time period.

Whil-e a particular preferred embodiment of the invention has beendescribed above, the invention contemplates such changes ormodifications therein as lie within the scope of the appended claims.

What is claimed is:

1. A timing circuit for actuating a load in accurate and predeterminedrelationship .to the occurrence of events in at least two distinct inputsystems, comprising in combination:

a unijunction transistor having an emitter and two bases and biasingmeans connected to one of said bases so that a predetermined bias ismaintained thereon;

means connecting one o-f said input systems to said one base whereby thebias on said one base can be modifled;

a first capacitor and a first charging circuit for said capacitor, saidfirst charging circuit being connected to the other input system;

a first discharging circuit for said first capacitor including aconnection to said emitter and thence through the other base of saidunijunction transistor;

a voltage limiting circuit connected to said first capacitor forlimiting the maximum charge thereon;

a second capacitor connected to said emitter and across a portion ofsaid discharging circuit to maintain con- 7 duction of said unijunctiontransistor until said first capacitor has discharged at least to apreselected minimum value;

a load connected to said discharging circuit; and a supplementalcharging circuit connected to said second capacitor for establishing aminimum charge thereon when said rst charging circuit is ineffective.

2. The device defined in claim 1 including: means connected to said rstcapacitor for normally blocking same from charging past said preselectedminimum level, said means being actuable for allowing said rst capacitor.tocharge past said minimum level, said minimum level of charge on saidrst capacitor being less'than said minimum charge on said secondcapacitor.

In a timing circuit for allowing conduction of a unijunction transistorhaving an emitter after a timed interval and upon application of apreselected signal, the combination comprising:

means for maintaining the voltage on said emitter at least above a rstminimum voltage, said rst minimum voltage being less than that requiredfor allowing conduction of said unijunction transistor;

a timing capacitor; charging means for charging said timing capacitor asa function of time;

blocking means actuable to block said charging means in order tomaintain the volta-ge on said timing capacitor below a preselectedsecond minimum, said second minimum being less than said first minimum;

unidirectional conducting means connecting said timing capacitor to saidemitter for allowing said timing capacitor to raise the voltage on saidemitter but preventing charging of said timing capacitor by a voltage onsaid emitter;

whereby deactuation of said blocking means allows said biasing meanscapable of providing a predetermined a rst capacitor;

voltage to said base;

series circuit comprising isolating means and a Second capacitor, saidisolating means being capa-ble of limiting the extent to which thevoltage across said iirst capacitor exceeds the voltage across saidsecond capacitor;

charging means for applying an increasing voltage across said firstcap-acitor and said series circuit;

switch means energizable for limiting the voltage applied by saidcharging means across said rst capacitor and said series circuit to apredetermined rst minimum level;

`further charging means for maintaining the voltage across said secondcapacitor above a second minimum level, said second minimum levelexceeding said 'first minimum level;

means for limiting the maximum voltage which can be applied by saidcharging means across said first capacitor and said series circuit whensaid switch means is de-energized, said maximum voltage exceeding saidsecond minimum level;

means connecting said second capacitor to said emitter for causingconduction of said unijunction transistor in response to application ofsaid preselected voltage to said base while said rst capacitor has saidmaximum voltage thereacross.

`5. A timing circuit for energizing a load subsequent to an event in oneinput system and in synchronism with an event in another input system,comprising the combination:

a source of D.C. potential and a pair of conductors connected toopposite sides of said D.C. source;

a lirst voltage divider connected to and between said conductors and aunijunction transistor having an emitter and a pair of bases, said basesbeing connected in said rst voltage divider at a point intermediate theends thereof for providing a constant DC. bias on said bases;

a timing capacitor and a time constant determining resistance in aseries path therewith, said series path Ibeing connected to and betweensaid conductors in parallel with said first voltage divider for chargingsaid capacitor at a predetermined rate independent of the rate ofcurrent How through said unijunction transistor;

conductive means connecting the side of said capacitor adjacent saidtime constant resistance to the emitter of said unijunction transistor;

a switch connected in parallel with said capacitor and to said resistorside thereof, said switch being closable for shunting said capacitor toprevent charging thereof above a preselected shunt charge level;

a second voltage divider connected to and between said conductor pair inparallel with said iirst voltage divider and a diode connected from anintermediate point on said second divider to said emitter, the anode ofsaid diode being connected to said emitter to limit the voltage on saidemitter to a maximum level below that required to cause conductionthrough said unijunction with said constant D.C. bias on said bases andto limit the charge on the capacitor to a corresponding maximum charge;

a third voltage divider connected to and between said conductor pair inparallel with said second voltage divider and a further diode connectedfrom an intermediate point on said third voltage divider to saidemitter, said intermediate point on said second voltage divider beingmaintained at a lower D.C. potential than said intermediate point onsaid third divider, the cathode of said fur-ther dio-de being connectedto said emitter for preventing the charge on said capacitor fromdropping below a constant, nonzero minimum charge corresponding to aminimum emitter voltage spaced below said maximum level, said minimumcharge level being at least as great as said shunt charge level;

a source of regularly spaced, negative pulses connected to thepositively biased one of said lbases for periodically lessening thepotential drop across said bases, said unijunction transistor beingcapable of conduction only upon coincidence of an emitter voltage levelsubstantially equal to said maximum voltage and one of said negativepulses, conduction of said unijunction transistor discharging saidcapacitor at least to said minimum level of charge;

a load connected to the other of said bases, said load including meansresponsive to conduction of said uni- `junction transistor through saidswitch for closing said switch;

whereby the minimum time required to energize said load as determined bythe charging time of said capacitor is constant in the face ofvariations of the source voltage and of the shunt voltage drop occurringacross the capacitor with the switch closed.

6. A timing circuit for energizing a load subsequent to an event in oneinput system and in synchronism with an event in another input system,comprising the combination:

a source of D.C. potential and a pair of conductors connected tooppositesides of said D.C. source;

a first voltage divider connected to and between said conductors and aunijunction transistor having an emitter and a pair of bases, said basesbeing connected in said rst voltage divider at a point intermediate theends thereof for providing a constant D.C. bias on said bases;

a timing capacitor and a time constant determining rel a voltagelimiting circuit connected to said emitter for limiting the maximumvoltage thereon; a load connected to said discharging circuit; and avoltage divider connected across said D.C. potential sistance in aseries path therewith, said series path source and a diode connected toan intermediate being connected to and Ibetween said conductors in pointthereon and to said timing capacitor for estabparallel with said firstvoltage divider for charging lishing a minimum nonzero charge thereonwhen said said capacitor at a predetermined rate; charging circuit isineffective;

conductive means connecting the side of said capacitor said voltagelimiting circuit `and supplemental charging adjacent said time constantresistance to the emitter circuit precisely ldetermining theI minimumtime of said unijunction transistor for placing a voltage required toeffect conduction of said unijunction on said emitter corresponding tothe charge on said transistor regardless of variations in said D C.supcapacitor; ply.

a switch connected in parallel with said capacitor, said i8. The circuitdefined in claim 7 including a switch switch Ibeing closable forshunting said capacitor to l5 connected in parallel with said capacitorand means prevent charging thereof above a preselected shunt renderingsaid switch path conductive as a result of concharge level; duction ofsaid unijiunction transistor whereby said cavoltage divider circuitryconnected to and between said pacitor can discharge through said switchto a predeterconductor pair in parallel with said first voltage minedvalue at least as low as said minimum charge redivider and adiodeconnected from one intermediate gardless of the characteristics of saidunijunction tranpoint on said voltage divider circuitry to saidemitsistor. ter, the anode of said diode being connected to said 9. .Atiming circuit for actuating a load subsequent to emitter to limit thevoltage on said emitter to a the occurrence of events in at least twodistinct input maximum level below that required to cause conducsystems,comprising in combination: tion through said unijunction with saidconstant a D.C. potential source;

D.C. bias on said ybases and to limit the charge on a unijuncticntransistor having an emitter and two the capacitor to a correspondingmaximum charge; bases and means connected between said bases and afurther diode connected from a further intermediate said D.C. potentialsource so that a predetermined point on said voltage divider circuitryto said emit- D.C. bias is maintained across said bases; ter, saidfurther intermediate point being maintained 30 means connecting one ofSaid input systems to one of a higher D.C. potential than said oneintermediate said bases whereby the .bias on said one base can be point,the cathode of said further diode being conlessened; nected to saidemitter for preventing the charge on a capacitor and a charging circuitfor said capacitor, said capacitor from dropping below a constant,nonsaid charging circuit being connected to the other `zero minimumcharge corresponding to a minimum input system; emitter voltage spaced.below said maximum level, a discharging circuit for said capacitorincluding a consaid minimum charge level being at least as great asnection from said capacitor to said emitter and said shunt charge level;thence through the other base of said unijunction a source of regularlyspaced, negative pulses connected transistor;

to the positively `biased one of said bases for perioda voltage dividerconnected across said D.C. source and ically lessening the potentialdrop across said bases, a diode having an anode connected to saidemitter said unijunction transistor being capable of conducand a cathodeconnected to an intermediate point ltion only upon coincidence of anemitter voltage on said voltage divider lfor maintaining the voltagelevel substantially equal to said maximum Voltage on said emitter below.a maximum value, said maxiand one of said negative pulses, conductionof said mum value being ybelow that requiredto cause conunijunctiontransistor discharging said capacitor at ducting of said unijunctiontransistor with said lbias least down to said minimum level of charge;across said bases;

a load connected to the other of said bases; a load connected to saidother base;

whereby the minimum time required to energize said said voltage dividerand diode precisely determining load as determined by charging time ofsaid capacithe minimum time required to efect conduction of tor isconstant in the face of variations of the source said unijunctiontransistor regardless of variations voltage and of the shunt Voltagedr-op occurring in said lD.C. supply. across the capacitor with theswitch closed.

7. A timing circuit for actuating a load in accurate and ReferencesClfed by the Examiner predetermined relationship to the occurrence ofevents in UNITED STATES PATENTS atleast two distinct input systems,comprising in combina- 2,937,289 5/1960 A1 rich et al. 307 885 U0-2,997,665 8/1961 syivan 307-88.5 a D9 Poienml smf 3,018,384 i/1962Zrubek 307-885 a umjunction transistor having an emitter and two bases p3,045,150 7/1962 Mann 307-885 and biasing means connected to said basesand to 3 092 729 6/1963 C 307 88 5 'd \D C. otential source so that apredetermined ray Sal .P h 3,127,522 3/1964 Thorndyke 307-885 DC blas.mamtamed .t rem l3,128,396 4/1965 Morgan 307-885 means connecting oneof said input systems to one base 3 206 x 612 5/1965 Swanekam et al 30788 5 thereby the bias on said one base can be modied; p

OTHER REFERENCES G. E. notes on the application of Silicon UnijunctionTransistor, by Sylvan, pages 48 and 59-6'4.

a timing capacitor and a charging circuit for said capacitor, saidcharging circuit :being connected to said [D C. potential source inresponse to an event in lthe other input system;

`a discharging circuit for said timing capacitor including a connectionfrom said timing capacitor to said emitter and thence through the otherbase of said unijunction transistor;

ARTHUR GAUS'S, Primary Examiner.

DAVID J. GALVIN, Examiner.

B. P. DAVIS, Assistant Examiner.

1. A TIMING CIRCUIT FOR ACTUATING A LOAD IN ACCURATE AND PREDETERMINEDRELATIONSHIP TO THE OCCURRENCE OF EVENTS IN AT LEAST TWO DISTINCT INPUTSYSTEMS, COMPRISING IN COMBINATION: A UNIJUNCTION TRANSISTOR HAVING ANEMITTER AND TWO BASES AND BIASING MEANS CONNECTED TO ONE OF SAID BASESSO THAT A PREDETERMINED BIAS IS MAINTAINED THEREON; MEANS CONNECTING ONEOF SAID INPUT SYSTEMS TO SAID ONE BASE WHEREBY THE BIAS ON SAID ONE BASECAN BE MODIFIED; A FIRST CAPACITOR AND A FIRST CHARGING CIRCUIT FOR SAIDCAPACITOR, SAID FIRST CHARGING CIRCUIT BEING CONNECTED TO THE OTHERINPUT SYSTEM; A FIRST DISCHARGING CIRCUIT FOR SAID CAPACITOR INCLUDING ACONNECTION TO SAID EMITTER AND THENCE THROUGH THE OTHER BASE OF SAIDUNIJUNCTION TRANSISTOR; A VOLTAGE LIMITING CIRCUIT CONNECTED TO SAIDFIRST CAPACITOR FOR LIMITING THE MAXIMUM CHARGE THEREON; A SECONDCAPACITOR CONNECTED TO SAID EMITTER AND ACROSS A PORTION OF SAIDDISCHARGING CIRCUIT TO MAINTAIN CONDUCTION OF SAID UNIJUNCTIONTRANSISTOR UNTIL SAID FIRST CAPACITOR HAS DISCHARGED AT LEAST TO APRESELECTED MINIMUM VALUE; A LOAD CONNECTED TO SAID DISCHARGING CIRCUIT;AND A SUPPLEMENTAL CHARGING CIRCUIT CONNECTED TO SAID SECOND CAPACITORFOR ESTABLISHING A MINIMUM CHARGE THEREON WHEN SAID FIRST CHARGINGCIRCUIT IS INEFFECTIVE.